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////  CFClean.v                                                   ////
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////////////////////////////////////////////////////////////////////JF


//This module provides a rising edge delay for glitchy signals
module CFClean(CFClock, In, Out);


input CFClock;
input In;
output Out;

reg [2:0]Hold;

//synthesis attribute INIT of Hold is 11;

always @(posedge CFClock)
begin
   if (In == 0) Hold[2:0] <= 3'b0;
else
   Hold[2:0] <= {Hold[1:0], 1'b1};
end

assign Out = Hold[2] && In;

endmodule